Montreal, Monday, September 14, 2026.

Three stories dominated the past seven days in computing, and — unusually — all three are stories about physics rather than marketing. Apple shipped the first 2-nanometre-class processor ever sold in a consumer phone, which means the gate-all-around transistor has finally left the research fab and entered a billion pockets. Memory prices continued their historic climb, because the atoms that store your data are being bid away by AI data centres, and that single supply-chain fact is now the largest single variable in what a laptop costs in Canada. And Microsoft published the largest security update in the company's history — 974 individual vulnerabilities in one Patch Tuesday — a number that tells you something structural about how modern software is assembled.

At PcHybrid we sell the hardware at the end of all these supply chains, so we care about the engineering underneath, not just the headline. This edition of Tech Science Daily explains what a gate-all-around transistor actually does, why a memory shortage in Korean fabs raises the price of a ThinkPad in Laval, and what 974 CVEs mean for the way you should be buying and managing business devices. Along the way we point to machines we currently have in stock, and we say plainly when a recommendation is about physics and when it is about price.

Today's Tech Radar

The ten stories our team tracked over the past week, ranked by how much they change what you should buy or how you should run your fleet.

Of these, three have enough scientific depth — and enough direct consequence for what you buy — to deserve a full explanation. We take them in order: the transistor, the memory, and the patch.

1. The gate-all-around era arrives: inside Apple's 2nm A20 Pro and the nanosheet transistor

A patterned silicon wafer. Each rectangular die will become a processor. Photo: Laura Ockel / Unsplash.

What Apple actually announced

On September 9, 2026, Apple introduced the A20 Pro and described it as the first smartphone processor built on a 2-nanometre-class process. It powers the iPhone 18 Pro, the iPhone 18 Pro Max, and Apple's new foldable. The headline specifications Apple gave are a six-core CPU with two performance cores up to 20% faster and four new efficiency cores; a redesigned seven-core GPU delivering up to 40% faster graphics; a 50% increase in memory bandwidth; and a dual 16-core Neural Engine — 32 cores in total — with roughly twice the AI throughput of the previous A19 Pro. Apple also claimed about 40% more sustained performance than the A19 Pro and roughly double the sustained performance of the A18 Pro of two generations ago.

That word "sustained" is doing a lot of work, and we will come back to it, because it is the part of the announcement that is really about thermodynamics rather than lithography.

Why "2 nanometres" is not a measurement

Let us be precise, because this is where most coverage becomes misleading. "2nm" is a marketing node name. It does not correspond to any physical dimension on the chip. No feature on a modern processor is two nanometres across; a silicon atom is roughly 0.2 nm in diameter, so a 2 nm gate would be about ten atoms wide and would not behave like a transistor at all. Node names stopped being measurements around the 22 nm generation. What they encode today is a generation of process technology with a characteristic density, performance and power profile.

The useful question is therefore not "how small is it" but "what changed in the transistor architecture". And this time, a great deal changed.

From FinFET to nanosheet: the actual engineering

A transistor is a switch. A voltage applied to a gate electrode controls whether current flows through a channel from source to drain. The entire art of chip scaling is maintaining the gate's authority over that channel as the channel shrinks.

For about a decade the industry used FinFET transistors. The channel was raised out of the wafer as a thin vertical fin, and the gate wrapped around it on three sides — left, right and top. Three-sided control was a huge improvement over the old planar design, where the gate only sat on top and the channel leaked underneath it.

But FinFETs have run out of room. As fins got thinner and shorter, the gate's grip weakened again. The physics problem is called short-channel effect: when source and drain get close enough, the drain's electric field begins to influence the channel directly, and the transistor starts to leak current even when it is supposed to be off. Leakage is pure waste — it becomes heat, drains batteries, and puts a floor under how low you can drop the operating voltage.

The fix at 2nm-class nodes is gate-all-around (GAA), implemented as stacked horizontal nanosheets. Instead of one vertical fin, the channel is formed from several very thin silicon sheets stacked one above another like the shelves of a bookcase, and the gate material is grown completely around each sheet — all four sides. TSMC describes N2 as its first GAA nanosheet node; Intel calls its own implementation RibbonFET and shipped it this January in Panther Lake / Core Ultra Series 3 on the 18A process.

Two consequences follow directly from the geometry:

Electrostatic control. Surrounding the channel on four sides rather than three means the gate field dominates the channel everywhere. Leakage in the off state drops sharply. TSMC quotes N2 as offering roughly 10–15% more performance at the same power, or 25–30% lower power at the same performance, versus its N3E predecessor, along with about 15% higher transistor density. Intel similarly cites around a 20% power reduction at matched performance from RibbonFET.

Tunable drive current. With FinFETs, the amount of current a transistor could carry was quantised: you added whole fins, so drive strength came in discrete lumps. Nanosheet width is a continuous design parameter. Designers can make a sheet wider where they need current and narrower where they need density. That flexibility is one reason GAA nodes tend to show their biggest gains in dense, highly optimised blocks like GPUs and neural accelerators — which is exactly where Apple's 40% graphics claim lands.

The next step: putting the power on the back

A modern processor has two networks laid over the transistors: signal wires that carry data, and power wires that deliver current. Historically both were built on the front side of the wafer, stacked in a dozen or more metal layers. Power rails are fat — they have to carry a lot of current without voltage droop — and they compete for space with the fine signal wiring below them, forcing awkward routing compromises and losing voltage along the way.

Backside power delivery separates them. The wafer is flipped, thinned, and a second wiring network is built on the underside purely to deliver power, connecting up to the transistors through vertical vias. Intel's implementation is called PowerVia and shipped with 18A; TSMC's is the Super Power Rail, arriving with the A16 node, a variant of N2P aimed at complex AI and HPC processors, from late 2026. The benefits are concrete: less resistive loss between the regulator and the transistor, a quieter power supply under fast load transients, and a decongested front side where signal routing can be denser and shorter.

For a buyer, backside power is one of the clearest reasons to expect meaningful efficiency gains in the 2027 laptop generation rather than the incremental single-digit improvements of the late FinFET years.

Sustained performance is a heat problem, not a silicon problem

Here is the part of Apple's announcement we find most instructive. Alongside the process change, Apple moved the memory so that it sits beside the silicon die rather than stacked in the thermal path above it, and connected the processor to a redesigned vapour chamber with roughly three times the surface area of the previous generation's cooling system.

That is a thermal-engineering decision, and it explains why the sustained-performance number (about 40% better than A19 Pro) is larger than the raw CPU number (about 20% on the performance cores). Peak clock speed is limited by silicon; sustained clock speed is limited by how fast you can move joules out of a package. A vapour chamber is a sealed cavity containing a small amount of working fluid: heat at the hot end boils the liquid, vapour spreads across the chamber almost instantaneously, condenses at the cooler end, and wicks back. It is an extremely effective heat spreader, and it is the reason a phone can now hold a high clock for minutes rather than seconds.

What this means when you are buying. Two devices with identical processors can differ by 20–30% in real sustained throughput depending on chassis design, and datasheets almost never tell you this. Thicker business laptops with proper dual-fan cooling — our Lenovo ThinkPad P16s Gen 4 with Ryzen AI 7 PRO 350, 32 GB and a 1 TB SSD is a good example, and it is in stock — will hold their clocks under a long compile or a long video export far better than a fanless ultraportable with the same nominal chip. If your work is bursty (email, documents, browsing), buy for weight and battery. If your work is sustained (rendering, compiling, large spreadsheets, local AI inference), buy for thermal capacity. That is the single most under-appreciated specification in the market.

The NPU question, in plain terms

Apple's 32-core Neural Engine, Qualcomm's 80-TOPS Snapdragon X2 Plus NPU, and the Ryzen AI and Intel Core Ultra NPUs in current Copilot+ laptops are all solving the same problem: matrix multiplication at low precision, cheaply.

A neural network's forward pass is overwhelmingly multiply-accumulate operations on tensors. A CPU core is a general-purpose machine with branch predictors, out-of-order execution and large caches — magnificent at unpredictable code, wasteful at predictable arithmetic. A GPU is better, being built for wide parallelism, but still carries graphics-specific machinery. An NPU (neural processing unit) strips all of that away: it is a dense grid of small multiply-accumulate units with local memory and a scheduler, running at low clock speed and low voltage. Because power scales roughly with the square of voltage, a wide-and-slow array beats a narrow-and-fast core by a large margin in operations per watt.

TOPS — trillions of operations per second — is the marketing unit, and it deserves scepticism. A TOPS figure is only meaningful alongside the numeric precision it was measured at (INT8 and INT4 give very different numbers) and the memory bandwidth feeding the array. An NPU starved of bandwidth is a fast engine with no fuel line. Apple's decision to raise memory bandwidth 50% alongside doubling neural throughput is the correct engineering pairing, and it is a useful lens for evaluating any AI PC claim.

Practically: Microsoft's Copilot+ tier requires an NPU of at least 40 TOPS, which is why features such as local Recall, Live Captions with translation, and Studio Effects run on these machines and not on older ones. If on-device AI matters to your organisation, the relevant in-stock options today include the Lenovo IdeaPad Slim 3 with Snapdragon X at the accessible end, the ThinkPad T14s Gen 6 with Ryzen AI 7 PRO 350 for a 14-inch business machine, and the Microsoft Surface Laptop 7 13.8" with Core Ultra 7 and 32 GB if you want maximum memory headroom in a thin chassis. If you would like help matching NPU capability to the software you actually run, you can request a free quote from our team and we will spec it against your workload rather than against a datasheet.

Industry context: three companies, one physics problem

It is worth noting how synchronised this transition is. TSMC began N2 volume production at the end of 2025 and is ramping through 2026, with N2P scheduled for the second half of this year and A16 — N2P plus the Super Power Rail — from late 2026. Intel launched 18A with RibbonFET and PowerVia in January. Samsung Foundry has its own GAA line, though reports suggest caution about 2nm yields influenced Samsung's decision to keep Qualcomm silicon in the Galaxy S26 Ultra rather than move it to in-house Exynos.

For a decade the leading edge was effectively a monopoly. Three credible GAA-capable foundries is a healthier structure, and over a two-to-three-year horizon it should mean better supply and more competitive pricing on flagship silicon. It does not, however, help with the problem in our next section — because the constraint there is not logic wafers at all.

2. The memory supercycle: why AI data centres are raising the price of your next laptop

Macro shot of a DRAM module. The black packages are the memory dies; everything else is routing and power. Photo: Liam Briese / Unsplash.

The numbers

According to TrendForce's latest pricing survey, conventional DRAM contract prices are set to rise 13–18% quarter-over-quarter in Q3 2026, with NAND flash contract prices up 10–15%. Those are large increases — and they represent a slowdown. The same survey notes roughly 60% quarter-over-quarter jumps in Q2 2026. Earlier in the year, forecasts of 50–55% quarterly increases were revised upward toward 90–95%, and spot prices moved far more violently still.

Critically, TrendForce attributes the Q3 deceleration not to improved supply but to demand destruction: consumer electronics manufacturers have reached the limit of what they can absorb and pass on. Memory is still short. Buyers have simply stopped being able to pay.

Downstream, PC makers including Dell, HP and Lenovo have raised prices in the region of 15–20%, and analysts expect both smartphone and PC unit shipments to contract this year.

Why DRAM is structurally different from logic

To understand why this shortage is so stubborn, you have to understand what makes DRAM unusual.

A DRAM cell is almost absurdly simple: one transistor and one capacitor — 1T1C. The capacitor holds a charge that represents a bit; the transistor gates access to it. That simplicity is what makes DRAM dense and cheap per bit. But the capacitor leaks. Charge bleeds away in tens of milliseconds, so the entire array must be read and rewritten continuously — the refresh operation that gives Dynamic RAM its name. Refresh costs power and steals bandwidth, and it is why DRAM is volatile: cut the power and the data evaporates within moments.

Scaling DRAM is therefore not the same problem as scaling logic. As cells shrink, the capacitor must keep enough capacitance to be reliably readable, which is why manufacturers build capacitors as extraordinarily deep, narrow trenches with aspect ratios of 100:1 or more — structures far taller than they are wide, etched into silicon with nanometre precision. This is a mechanical and chemical engineering challenge as much as a lithographic one, and it is the reason DRAM density improves more slowly than logic density. There is no Moore's Law rescue coming for DRAM supply.

The HBM diversion

Now add AI. Training and inference on large models are bandwidth-bound, not compute-bound: the accelerator can multiply far faster than memory can feed it. The industry's answer is High Bandwidth Memory — HBM — in which multiple DRAM dies are stacked vertically and connected by through-silicon vias, vertical copper columns punched straight through the silicon. The stack sits on an interposer millimetres from the GPU, and communicates over an extremely wide, relatively slow bus. Width buys bandwidth at far lower energy per bit than driving signals across a motherboard.

NVIDIA's Vera Rubin platform, in full production since its CES 2026 launch, pairs Rubin GPUs using HBM4 with a Vera CPU, NVLink 6 switching at 3.6 TB/s between GPUs, and co-packaged optical Ethernet. Each GPU is rated around 2,300 W, which is why the platform requires liquid cooling outright — air simply cannot remove that heat flux from that area.

The supply consequence is direct. HBM uses the same DRAM wafers, the same fabs and the same tools as the DDR5 in your laptop — but it consumes several dies per stack, requires additional stacking and bonding steps, suffers lower yields, and sells at a dramatically higher margin. Samsung, SK hynix and Micron have reallocated capacity accordingly. Every HBM stack shipped to a data centre is several laptops' worth of DRAM not made. SK hynix has publicly warned the imbalance may persist well beyond the end of this decade.

What this means for buyers, concretely

We want to be careful here, because this is where honest advice matters more than a sales pitch.

Specify memory generously at purchase, not later. This is the single most consequential change to buying strategy this year. Historically the smart move was to buy a modest configuration and upgrade RAM in two years, when it would be cheaper. That logic has inverted. Prices are forecast to keep climbing through at least 2027, and most modern thin-and-light laptops solder their LPDDR memory to the board — it is physically not upgradeable at any price. If a machine will serve for four or five years, the 32 GB configuration bought today is likely to be both the cheaper and the only available option. Our ThinkPad T14 Gen 5 with Ryzen 7 PRO 8840U, 32 GB and 512 GB is in stock in volume and is a sensible landing point for that logic.

Distinguish refresh cycles from upgrade cycles. If your fleet is running well, this is not an attractive year to replace it for marginal gains. If machines are genuinely at end of life — out of warranty, out of Windows support, or thermally degraded — deferring will most likely cost more, not less. Volume stock purchased under earlier contracts is the temporary exception, and it does not last.

Be realistic about storage. NAND flash is under the same pressure, with client SSD pricing moderated only because PC makers stockpiled inventory in the first half of the year. A 512 GB SSD today costs meaningfully more than it did eighteen months ago, and cloud storage plus a smaller local drive is a defensible architecture for many office roles.

Consider whether a tablet does the job. For field staff, kiosks, signage front-ends and point-of-sale, a tablet often delivers the required function at a fraction of the memory footprint — and therefore a fraction of the exposure to DRAM pricing. We have the Samsung Galaxy Tab A11+ (11-inch, 6 GB / 128 GB) in stock at 100 units for cost-sensitive deployments, the Galaxy Tab S10 Lite when you need a better panel and S Pen support, and the Lenovo Tab K11 Gen 2 (11-inch 2.5K, 8 GB) as a well-balanced middle option. For rugged field work, the Panasonic Toughbook 33 MK4 remains in stock in small quantity.

If you are planning a fleet purchase and want an honest read on whether to buy now or wait, request a free quote from our team — we will tell you which configurations we hold at what price and where we think the market is heading, including when the answer is "don't buy yet".

A note on what economists call this

Memory has always been cyclical. The classic pattern is a capacity glut, price collapse, investment freeze, demand recovery, shortage, price spike, and renewed investment — a cycle typically running three to four years. What makes 2026 unusual is that the demand shock is not a consumer product cycle but a capital-expenditure boom in data centres, funded by companies with very deep balance sheets and very little price sensitivity. That combination — inelastic demand meeting inelastic supply — is precisely the recipe for sustained high prices, and it is why forecasts now extend the imbalance into 2027 and beyond rather than the usual handful of quarters.

3. Nine hundred and seventy-four: what Microsoft's record Patch Tuesday tells us

Endpoint security is now a patch-latency problem more than a perimeter problem. Photo: FlyD / Unsplash.

The scale of it

On September 8, 2026, Microsoft released fixes for 974 CVEs — the largest single Patch Tuesday in the company's history. Of those, 113 were rated Critical, roughly 20 were assessed as potentially wormable, 723 affected Windows itself, and 222 affected the Office suite, including 111 in Office 2016 alone.

Two were zero-days already being exploited in the wild, and both are privilege-escalation flaws:

• CVE-2026-85880 — a heap buffer overflow in the Windows Advanced Local Procedure Call (ALPC) subsystem, allowing a local attacker to obtain SYSTEM privileges.
• CVE-2026-81963 — an improper link resolution before file access ("link following") defect in the Windows Update stack, the component responsible for installing updates.

The science of the two bugs

These are worth understanding because they are archetypes.

A heap buffer overflow occurs when a program writes more data into a dynamically allocated memory region than that region can hold. The surplus spills into adjacent heap memory, which typically contains allocator metadata and pointers belonging to other objects. An attacker who controls the overflowing data can overwrite a function pointer or an object's virtual method table and redirect execution. ALPC is the high-speed message-passing mechanism Windows components use to talk to each other, and it necessarily runs at high privilege while accepting input from lower-privileged processes — which is exactly why memory-safety bugs there are so valuable to attackers. Modern mitigations such as ASLR, heap cookies and Control Flow Guard raise the difficulty considerably, but they are probabilistic defences, not proofs.

A link-following flaw exploits the gap between checking a path and using it. A privileged process resolves a filename, validates it, and then opens it. If an attacker can replace that path with a symbolic link or junction pointing somewhere else in the instant between the check and the use, the privileged process writes to a location the attacker chose. This class is known as TOCTOU — time-of-check to time-of-use — and it is a race condition, not a memory bug. The irony of finding one in the Windows Update stack, a component that by design runs at maximum privilege and manipulates files all over the system, is not lost on anyone.

Neither of these gives an attacker initial access. Both are the second stage: an attacker who has already achieved code execution as a normal user — through a phishing attachment, a browser exploit, a malicious package — uses a privilege-escalation flaw to become SYSTEM, and from there to disable defences, harvest credentials and move laterally. This is why "it's only a local privilege escalation" is a dangerous thing to say out loud.

Why 974 is a structural number

Nine hundred and seventy-four vulnerabilities in one month is not a sign that Microsoft's engineering collapsed. It is a sign of three converging trends.

First, the attack surface genuinely grew. Windows now ships with AI features, expanded virtualisation, new hardware abstraction layers, and decades of preserved compatibility code. More code means more defects, more or less linearly.

Second, discovery got much faster. Automated fuzzing — bombarding software with malformed inputs and watching for crashes — has been industrialised, and machine-learning-assisted code analysis is now routinely used by both vendors and researchers. We are not necessarily writing worse software; we are finding existing defects far more efficiently.

Third, memory-unsafe languages remain dominant in system code. Microsoft's own historical analysis put roughly 70% of its security patches in the memory-safety category — buffer overflows, use-after-free, type confusion. These are whole categories of bug that languages like Rust make structurally impossible; the industry is migrating, but decades of C and C++ do not vanish quickly.

The same week reinforced the pattern elsewhere: GitLab disclosed a CVSS 10.0 path-traversal flaw in its repository commits API allowing unauthenticated arbitrary file reads, with in-the-wild probing reported from September 11; Check Point disclosed two 9.8-rated flaws in its security gateways; and CISA added seven actively exploited vulnerabilities to its Known Exploited Vulnerabilities catalog on September 2, affecting SonicWall SMA 1000 appliances, JFrog Artifactory, Sangoma Switchvox, and the AI-workflow tools Kestra and LiteLLM. Microsoft and Wiz both documented attackers using those AI-infrastructure flaws to plant reverse shells, deploy cryptocurrency miners, and steal model-provider API keys.

That last detail is the genuinely new thing this year: AI gateways, vector databases and agent frameworks have become a first-class attack surface, and they are frequently deployed by teams outside traditional IT governance.

What a business should actually do

The practical conclusions are unglamorous and effective.

Measure patch latency, and treat it as your primary metric. The number that matters is the median time between a vendor's release and deployment across your fleet. If that number is measured in weeks, no amount of security software compensates. CISA's own binding directives gave U.S. federal agencies days, not weeks, for the September KEV additions — a reasonable benchmark for anyone.

Prioritise by exploitation, not by CVSS. You cannot triage 974 items by severity score alone. The CISA KEV catalog is a free, authoritative list of what is actually being exploited. Patch those first, always.

Keep hardware current enough to receive updates. A device that cannot run a supported OS cannot be patched, and it is an unacceptable risk on a business network regardless of whether it still boots. Modern business machines — for example the ThinkPad T16 Gen 4 with Ryzen AI 5 PRO 340, in stock in volume — ship with TPM 2.0, firmware-level protections, virtualisation-based security and hardware-enforced stack protection enabled by default. These raise the cost of exactly the exploitation classes described above.

Inventory your AI tooling. If anyone in your organisation has stood up an LLM gateway, a vector store or an agent framework, it is production infrastructure holding production credentials. It needs the same patching, network segmentation and secret rotation as any other server.

Enforce phishing-resistant authentication. Privilege escalation needs an initial foothold, and stolen credentials remain the most common one. Hardware security keys implementing FIDO2 and WebAuthn eliminate credential phishing as a category, because the cryptographic challenge is bound to the origin and simply will not answer to a lookalike domain.

If you would like a structured review of your endpoint fleet — patch posture, hardware eligibility for current OS baselines, and where your genuine exposure sits — request a free quote from our team. We will give you a written assessment, and we will say when the correct answer is that you do not need to buy anything.

Bonus: why Micro RGB matters for the screens you buy next

Story #10 on our radar deserves a short technical note, because it will shape the large-format display market over the next two years.

Almost every LCD television and commercial panel sold today works the same way: a backlight of blue LEDs excites a layer of phosphor or quantum dots to produce broad-spectrum white light, which then passes through a liquid crystal shutter and a colour filter array. Every one of those stages throws away light, and the colour filter in particular is subtractive — it produces red by absorbing everything that is not red.

Samsung's Micro RGB approach, which it is expanding in 2026 across 55-, 65-, 75-, 85-, 100- and 115-inch classes, replaces the white backlight with discrete red, green and blue LEDs smaller than 100 micrometres, each individually driven. The light is generated in the correct colour rather than filtered into it. Samsung states that the resulting Micro RGB Precision Color 100 system, verified by VDE, achieves 100% of the BT.2020 wide colour gamut — the ultra-wide colour space defined for ultra-high-definition television, which conventional quantum-dot displays typically cover only partially.

It also improves local contrast. Because the backlight is composed of a very large number of individually controllable emitters, the dimming zones become far finer, reducing the "halo" or blooming artefact visible around bright objects on dark backgrounds in conventional LED-backlit panels.

This technology sits at the premium end today. For commercial deployment — meeting rooms, retail, digital signage, classrooms — the practical requirements are different and well served by current panels: 24/7 duty rating, anti-glare coating, adequate sustained brightness, and dust ingress protection. We hold the Samsung QM85C 85-inch UHD, 500 nit, non-glare, IP5X-rated for 24/7 operation in stock, along with the 75-inch QMC series and the Samsung Crystal UHD Signage QMC. For desktop work, the ViewSonic 32-inch 4K UHD IPS monitor with 65 W USB-C is in stock in quantity and remains, in our view, the most useful single upgrade most office users can make — one cable for video, data and laptop charging.

Glossary of the Week

Setup at a Glance

Everything below is in stock at PcHybrid as of today's publication. Quantities move quickly; confirm with us before committing to a fleet order.

Closing thought

The through-line in all three of today's deep dives is that the constraints on computing have moved from the abstract to the physical. Transistor performance is now limited by electrostatics and heat flux, not by lithography alone. Device pricing is limited by capacitor trench etching and wafer allocation, not by demand. And security is limited by how quickly an organisation can deploy a patch, not by how good its firewall is.

None of these are problems you solve by buying the highest number on a spec sheet. They are problems you solve by matching real engineering characteristics to your actual workload — and, increasingly, by timing purchases sensibly in a distorted market.

That is the part we can help with. If you are planning a refresh, sizing a fleet, specifying a meeting room, or simply trying to work out whether this is a good year to buy at all, request a free quote from our team. We will look at what you actually run, tell you what we hold in stock and at what price, and give you our honest read — including when the right answer is to wait.

See you tomorrow.

Sources & Further Reading

Apple A20 Pro and the 2nm transition: 9to5Mac — Apple announces A20 Pro chip with 2nm design; MacRumors — Apple unveils A20 Pro as first 2nm smartphone chip; Android Headlines — Apple enters the 2nm era; MacRumors — Apple's September 2026 event guide. Foundry and process technology: Tom's Hardware — TSMC begins volume production of 2nm-class chips; TechSpot — TSMC's N2 process enters volume production; igor'sLAB — Intel Panther Lake and 18A; ServeTheHome — Intel Core Ultra Series 3 launch. Memory market: Tom's Hardware — Memory price surge begins to cool (TrendForce Q3 2026 data); IDC — Global memory shortage crisis; CNBC — AI memory is sold out; The Register — DRAM prices expected to double. AI infrastructure: NVIDIA — Inside the Vera Rubin platform; Data Center Knowledge — NVIDIA launches Rubin. Security: SecurityWeek — Microsoft patches record 974 vulnerabilities; The Hacker News — Record 974 flaws, two exploited Windows zero-days; SOCRadar — September 2026 Patch Tuesday analysis; Zero Day Initiative — September 2026 security update review; The Hacker News — CISA adds seven exploited flaws; CISA — Known Exploited Vulnerabilities catalog addition; The Hacker News — GitLab CVSS 10 file-read flaw. Displays and devices: Samsung Newsroom — Micro RGB TV lineup for 2026; Samsung Global Newsroom — 130-inch Micro RGB TV; Neowin — Snapdragon X2 Plus for mainstream Copilot+ PCs; Android Authority — Best of IFA 2026; SamMobile — Galaxy S26 chipset split explained. Photos: Unsplash (free commercial license).

Tech Science Daily is published by PcHybrid, Montreal. We explain the engineering behind the week's technology news and connect it to equipment we actually stock. Specifications and stock levels cited are accurate at time of publication and are subject to change.