Montreal, Wednesday, August 26, 2026. Three stories dominated the technology wires overnight, and although they look unrelated on the surface — a memory shortage, a desktop computer, and a Windows driver patch — they are actually three views of the same underlying shift. Artificial intelligence has stopped being a software story and become a physics and manufacturing story. It is consuming silicon wafers, electricity, and memory dies at a rate the supply chain was never built to absorb, and the consequences are now visible on price tags, in product specifications, and in the security posture of every machine on your network.

Yesterday Apple announced a Mac mini built around the M6, the company's first processor manufactured on a 2-nanometre process, and quietly raised the entry price by $100. Analysts at IDC are forecasting that average PC prices will climb by as much as 8% across 2026, driven almost entirely by DRAM and NAND scarcity. And two weeks ago Microsoft shipped one of the largest Patch Tuesday releases in its history, closing more than four hundred vulnerabilities including a kernel-level flaw that state-linked attackers were already exploiting.

At PcHybrid we sell the hardware at the end of that chain — laptops, desktops, workstations, tablets, phones, commercial displays, memory, and storage — so our job today is not to repeat the headlines but to explain the engineering beneath them, and to translate that engineering into decisions you can actually act on. Below you will find our shortlist of the ten stories that mattered most this week, followed by three deep dives written for readers who want to understand why, not just what.

Today's Tech Radar

Our editorial shortlist for August 26, 2026. Each entry was cross-checked against at least two independent sources.

Deep Dive 1 — The Memory Crunch: Why a DDR5 Kit Costs What a Laptop Used To

A SODIMM memory module. The eight black packages are DRAM dies; the gold fingers carry the data bus. Photo: Franck V. / Unsplash.

If you have shopped for RAM this summer you already know the number that shocked the industry: a 64 GB DDR5 kit that sold for a couple of hundred dollars in mid-2025 was fetching well over a thousand by August 2026. In Germany, the widely-followed 3DCenter retail price index for DDR5 reached roughly 486% of its July 2025 baseline. Contract DRAM prices, which are what manufacturers actually charge system builders, are forecast by TrendForce to rise a further 13–18% quarter over quarter in Q3 2026. Some vendors have started shipping pre-built desktops with the memory slots empty and letting the customer source their own.

This is not a temporary logistics hiccup. It is a structural reallocation of manufacturing capacity, and understanding it requires a short trip into how memory is actually made.

What a DRAM cell physically is

Dynamic random-access memory stores a bit in the simplest possible structure: one transistor and one capacitor, usually written 1T1C. The capacitor holds a small quantity of electric charge — charged means one, discharged means zero — and the transistor acts as a gate that connects the capacitor to a shared wire called the bit line when the row is selected.

The word "dynamic" is doing real work in that name. Capacitors leak. A DRAM cell loses its charge in a matter of milliseconds, so the memory controller must read every row and write it back, over and over, thousands of times per second. That refresh cycle is why DRAM burns power even when your computer is idle, and it is why DRAM cannot simply be scaled down the way logic transistors can. Shrink the capacitor and it holds less charge; hold less charge and the difference between a one and a zero becomes harder to sense above thermal noise. Manufacturers have responded with extraordinary three-dimensional capacitor geometries — deep trenches and high-aspect-ratio pillars that maximise plate area within a shrinking footprint — but the physics resists. This is why DRAM density improves far more slowly than logic density, and why every extra gigabyte genuinely costs silicon area.

The HBM diversion

Now add the AI accelerator. A modern training GPU is not limited by arithmetic; it is limited by how fast it can feed its arithmetic units. The industry's answer is High Bandwidth Memory, or HBM: instead of placing memory chips beside the processor on a circuit board, HBM stacks eight, twelve, or sixteen DRAM dies vertically and connects them with thousands of vertical copper channels called through-silicon vias. The stack sits on the same package substrate as the GPU, millimetres away, which slashes the distance a signal must travel and allows a bus thousands of bits wide instead of the 64 bits of a conventional DIMM channel.

The result is spectacular bandwidth — and terrible efficiency in wafer terms. Stacking, thinning, drilling and bonding those dies means low yields, and every HBM stack consumes several times the wafer area of the equivalent capacity in commodity DDR5. According to industry analysis, HBM absorbed roughly 23% of global DRAM wafer output in 2026, up from about 8% in 2024. Nearly a quarter of the world's DRAM manufacturing capacity is now devoted to a product category that ordinary consumers never buy directly.

That capacity has to come from somewhere, and it comes from the lines that used to make the DDR5 in your laptop. Compounding the squeeze, hyperscale cloud operators have locked in long-term supply agreements for server DRAM and enterprise SSDs, which means those orders are scheduled first. At least one major NAND manufacturer has confirmed its entire 2026 production was pre-sold. Micron has signalled that supply-demand conditions will remain tight beyond calendar 2026, and TrendForce does not expect meaningful new capacity before late 2027 or 2028.

Why NAND is caught in the same net

NAND flash — the technology inside every SSD — has a different physics but a similar bottleneck. NAND stores charge in a floating gate or charge-trap layer that retains its state without power. To increase density without shrinking cells further, manufacturers went vertical: 3D NAND stacks memory layers on top of each other, now well past two hundred layers in leading products, and etches a single hole straight down through the entire stack to form a string of cells. Each additional layer adds cost, complexity, and a longer, harder etch.

Manufacturers also squeeze more bits into each cell — TLC stores three bits per cell by distinguishing eight distinct charge levels, QLC stores four by distinguishing sixteen. Every additional level narrows the voltage margin between states, which reduces endurance and increases the error-correction burden. When AI data centres buy enterprise SSDs by the exabyte, the consumer market gets the leftovers, and prices follow.

What this means when you buy a computer this quarter

There is a counter-intuitive lesson here that is worth stating plainly: in a memory shortage, a machine already sitting in a warehouse with its RAM and SSD installed is a hedge. Its bill of materials was locked at an earlier price. The next production run will not be.

A second lesson: buy the memory configuration you need for the life of the machine, not the one you plan to upgrade later. This is doubly true for modern thin-and-light laptops, where LPDDR5X memory is soldered directly to the mainboard — or, in the case of Intel's Lunar Lake and Apple's M-series designs, packaged alongside the processor itself and physically impossible to change.

Concretely, for a Windows fleet the sweet spot right now is 16 GB for general office work and 32 GB for anyone running virtual machines, large datasets, video editing, or local AI models. In our own catalogue, the Dell Pro 16 Plus PB16250 with Core Ultra 7 265U, 16 GB and a 512 GB SSD is our deepest-stocked business notebook and represents that 16 GB baseline at pre-crisis pricing. If you need headroom, the Dell Pro 14 Plus PB14250 with 32 GB gets you there in a 14-inch chassis. For workstation-class memory, the HP Z2 G9 tower with a Core i7-14700, 64 GB and a 1 TB SSD is the kind of configuration that would be materially more expensive to build from parts today.

On storage, the same logic applies. A Samsung 990 PRO 1 TB PCIe Gen4 NVMe drive bought now is a component whose replacement cost is rising, not falling. And if you maintain older DDR4 systems that you would rather refresh than replace, modules such as the Axiom 8 GB DDR4-3200 UDIMM for HP extend the useful life of hardware you already own — which, in this market, is the cheapest gigabyte you will find. If you are planning a fleet refresh and want help modelling the cost difference between buying now and waiting, you can request a free quote from our team.

Deep Dive 2 — Two Nanometres and the Neural Engine: What Apple's M6 Actually Changes

A processed silicon wafer at a back-end assembly station. Each rectangle is a die that will become a single chip. Photo: L N / Unsplash.

On August 25 Apple announced a refreshed Mac mini, the first update to the compact desktop in nearly two years. The base model carries the M6, described as Apple's first 2-nanometre processor; a higher tier uses the M5 Pro. Pre-orders opened immediately with deliveries beginning September 22. The M6 configuration starts at $899 with 16 GB of unified memory and 256 GB of storage — a $100 increase over the outgoing M4 entry model, which is itself a small monument to the memory story above.

The specifications worth dwelling on are architectural. The M6 has a 12-core CPU, two more than M4 and M5, and it is Apple's first design to use three distinct core types simultaneously: two "super" cores, four performance cores, and six efficiency cores. Apple also brings its Neural Accelerators to the base Mac mini for the first time, claiming up to four times faster AI performance and twice the graphics throughput of the M4. Memory bandwidth rises to 170 GB/s, and the chassis gains Thunderbolt 5 and improved Ethernet.

What "2 nanometres" actually measures — and what it doesn't

Let us dispose of a common misconception immediately. The "2 nm" in a process node name does not describe the physical length of anything on the chip. It has not corresponded to a measurable dimension since roughly the 22 nm era. It is a marketing generation label, and different foundries use it to mean somewhat different things.

What it does reliably signal is a step forward in transistor density and, usually, transistor architecture. The relevant change at this generation is the shift from FinFET to gate-all-around nanosheet transistors. In a FinFET, the silicon channel through which current flows is a thin vertical fin, and the gate — the electrode that switches the transistor on and off — wraps around it on three sides. In a gate-all-around nanosheet device, the channel is instead a stack of horizontal silicon ribbons, and the gate material is deposited completely around all four sides of each ribbon.

Why does surrounding the channel matter? Because a transistor's fundamental problem at small scale is leakage. When the gate is off, you want zero current to flow; in practice, a small subthreshold current always leaks through, and that leakage current is what makes a phone warm in your pocket while doing nothing. The more of the channel's perimeter the gate controls, the more completely it can pinch off that current. Full electrostatic control means you can operate the transistor at a lower supply voltage for the same switching speed — and since dynamic power scales with the square of voltage, a modest voltage reduction produces a large power saving. That is the real currency of a node transition: not raw speed, but performance per watt.

Nanosheets have a second useful property. In a FinFET, the amount of current a transistor can drive is quantised — you get more drive current by adding whole fins, in discrete jumps. With nanosheets, the designer can vary the width of the ribbons continuously, tuning each transistor between high-drive and low-leakage behaviour. For a chip like the M6 that mixes super cores, performance cores and efficiency cores on one die, that flexibility is precisely what is needed.

The three-tier CPU and why heterogeneity won

For four decades the industry improved processors mainly by making one kind of core faster. That approach ran into a wall known as the end of Dennard scaling: transistors kept getting smaller, but their power density stopped falling proportionally, so you could no longer light up every transistor at full clock speed without melting the package.

The escape route was heterogeneity. Instead of one core type optimised for a compromise between speed and efficiency, build several kinds and route each task to the right one. Efficiency cores use shorter pipelines, simpler branch prediction, and narrower issue widths, and they handle background work — mail sync, indexing, notifications — at a fraction of the energy per instruction. Performance cores run the app you are actually looking at. A "super" core, sitting above both, targets the single-threaded bursts that determine how fast an application feels: launching, compiling, applying a filter.

The operating system scheduler decides who runs where, and getting that decision right is as much of an engineering achievement as the silicon itself. This is the same architectural philosophy behind Intel's performance and efficient cores and behind Arm's big.LITTLE lineage — Apple has simply added a third rung to the ladder.

Neural accelerators: matrix multiplication, close to memory

The claim of "4× faster AI performance" needs unpacking. Neural network inference is dominated by one operation: multiplying large matrices and accumulating the results. A general-purpose CPU core does this with vector instructions, a handful of values at a time, spending most of its energy on instruction fetch, decode, and register file access rather than on the arithmetic itself.

A neural processing unit removes that overhead. It implements a large grid of multiply-accumulate units — often arranged as a systolic array, where each cell passes its result directly to its neighbour rather than writing back to a register file — and it operates on reduced-precision numbers. Neural networks tolerate low precision remarkably well, so instead of 32-bit floating point, an NPU works in 16-bit, 8-bit integer, or in some newer designs 4-bit formats. Halving the bit width roughly quarters the area of a multiplier and proportionally reduces the energy per operation and the memory traffic required to keep it fed.

The last point is the important one, and it connects directly back to Deep Dive 1. Running a large language model locally is overwhelmingly a memory-bandwidth problem: for each token generated, the processor must stream the model's weights from memory. Apple's unified memory architecture, where CPU, GPU and NPU all address the same physical pool at 170 GB/s, exists precisely to avoid copying data between separate memory spaces. It is also why a machine's memory capacity, not its clock speed, determines which models it can run at all.

Buying advice: what an NPU is worth to you today

The honest assessment is that on-device AI acceleration is currently a hedge rather than a necessity for most users. The features that genuinely use it — live transcription, background blur and noise suppression in video calls, semantic search across local files, generative image editing, and increasingly on-device assistants — are useful but not yet load-bearing for typical office work. What an NPU buys you is that these features run without a round trip to a cloud service, which means they work offline, they do not consume bandwidth, and your data does not leave the device. For organisations handling confidential material, that last property is often the deciding argument.

In the Windows world, the equivalent hardware is the Copilot+ PC class, which requires an NPU rated at 40 or more TOPS. If you want that capability today, the Dell Pro 16 Plus PB16250 Copilot+ notebook with Core Ultra 7 268V, 32 GB and vPro pairs Intel's Lunar Lake NPU with the 32 GB of memory that local models actually need. On the Arm side, the Dell Latitude 5455 with Snapdragon X Plus delivers the same Copilot+ class with the multi-day battery life that Arm designs are known for. If your workload is heavy on GPU compute rather than NPU inference — 3D rendering, simulation, model fine-tuning — the Lenovo Legion T7 with a Core Ultra 9 285K, 64 GB and a 1 TB SSD is the better tool, and its 64 GB of memory is exactly the sort of configuration that is becoming expensive to replicate.

For fleets where the AI question is genuinely premature, a compact and inexpensive machine remains the rational purchase. The Lenovo ThinkCentre neo 50q Gen 4, an eight-core i5-13420H tiny desktop, is our highest-volume stocked system and handles browser-and-Office workloads without paying for silicon you will not use. For mobile field work and digital signage front-ends, the Samsung Galaxy Tab A9+ 11-inch remains the value choice, and for staff who need a large-screen device that folds into a pocket, the Galaxy Z Fold7 with 12 GB of RAM and 512 GB of storage is in stock in limited quantity.

Deep Dive 3 — Inside CVE-2026-68820: How a Race Condition Becomes a Rootkit

Endpoint security is now a patch-cadence problem more than a product-selection problem. Photo: Ed Hardie / Unsplash.

On August 11, 2026, Microsoft published one of the largest Patch Tuesday releases on record. Depending on how the vendors counted bundled advisories, the tally ran between roughly 394 and 421 CVEs, with something on the order of forty rated Critical. The distribution across products was itself instructive: hundreds of fixes in Windows, close to a hundred in Office, dozens in SharePoint Server and developer tooling, plus fixes in Azure, Exchange and Defender.

One entry mattered more than all the others combined, because attackers were using it before the fix existed. CVE-2026-68820 is an elevation-of-privilege vulnerability in AFD.sys — the Ancillary Function Driver for WinSock — that allows a local attacker to escalate to SYSTEM. Check Point researchers reported that it was exploited by North Korean actors to deploy a kernel-mode rootkit in a fresh wave of the long-running Operation Dream Job campaign. CISA subsequently confirmed the flaw as exploited in the wild.

What AFD.sys is and why it sits in the kernel

When an application on Windows opens a network socket, it does not talk to the network card directly. It calls into the Winsock library in user space, which in turn hands the request to AFD.sys, a driver running in kernel mode that translates socket operations into calls on the underlying transport stack. Essentially every piece of software that touches the network — your browser, your mail client, your VPN, your update service — passes through it.

That is what makes it such an attractive target. Windows enforces a hard boundary between user mode, where applications run with limited privileges, and kernel mode, where the operating system core runs with unrestricted access to memory and hardware. Any driver reachable from user mode is a doorway through that boundary, and a bug in one gives an attacker a way to execute code on the privileged side. AFD.sys is reachable by unprivileged code by design, since ordinary applications must be able to open sockets. It has consequently been the subject of multiple privilege-escalation vulnerabilities over the years.

Use-after-free, explained without jargon

The specific bug class here is a use-after-free arising from a race condition, and the mechanism is worth understanding because it recurs constantly across operating systems.

Think of a kernel memory object as a hotel room. When a component needs to track some state — say, the details of an open socket — it allocates a room and keeps the key, which in software terms is a pointer holding the room's address. When it is finished, it checks out: the room is freed and returned to the allocator so that some other part of the system can use it. The critical rule is that once you check out, your key is no longer valid. Anyone who keeps using an old key is going to walk into a room that now belongs to someone else.

A use-after-free is exactly that: code that dereferences a pointer to memory that has already been released. Sometimes this simply crashes. But an attacker who controls timing can do something far more dangerous. Between the moment the object is freed and the moment the stale pointer is used, the attacker triggers a fresh allocation of the same size — a technique known as heap grooming or heap spraying — so that the allocator hands the same block of memory back, now filled with attacker-chosen bytes. The stale pointer then reads a data structure the attacker wrote. If that structure contains a function pointer, the kernel calls an address of the attacker's choosing, in kernel mode.

The "race condition" part explains why the bug existed at all. Modern kernels are heavily multithreaded, and multiple threads can operate on the same socket state concurrently. Correctness requires locking: before touching shared state, a thread must acquire a lock so that no one else can modify or free it mid-operation. In CVE-2026-68820, the synchronisation between concurrent socket operations was incomplete, leaving a narrow window in which one code path could free an object while another was still holding a reference to it. That window may be microseconds wide, but an attacker does not need to hit it on the first attempt — they simply run the same operation in a tight loop, thousands of times per second, until the timing lines up.

From SYSTEM to rootkit

Elevation of privilege is rarely the first stage of an attack; it is the second. The attacker needs code execution on the machine already, typically via phishing — and Operation Dream Job is precisely a phishing campaign, built around fake recruiter approaches and bogus job offers aimed at engineers and defence-sector staff. What CVE-2026-68820 provides is the escalation from an ordinary user account to SYSTEM, and from SYSTEM into the kernel itself.

That final step matters enormously. Endpoint detection and response software runs with high privilege, but it is still software running on top of the kernel. Code executing inside the kernel can unhook the callbacks that EDR products rely on, hide processes from enumeration, filter file-system and registry queries, and intercept network traffic below the level at which any user-mode monitor can observe it. A kernel-mode rootkit does not merely evade detection; it can make the machine report a clean state indefinitely. Recovering trust in such a system generally means reimaging it.

What defenders should actually do

The uncomfortable trend visible in this month's data is the collapse of the window between disclosure and exploitation. Analysts noted, for example, that a SAP Commerce Cloud vulnerability disclosed in the same period was under active attack within seventy-two hours. A monthly patch cycle with a two-week testing tail is no longer a defensible posture for internet-facing or high-value endpoints.

Practical measures, in rough order of impact:

• Patch AFD.sys immediately across every Windows endpoint. There is no configuration workaround for a driver that every networked application uses.
• Separate patch rings. Test on a small representative pilot group within 24–48 hours, then move to broad deployment, rather than testing the entire fleet before deploying to any of it.
• Reduce the initial-access surface. Escalation bugs need a foothold. Phishing-resistant multi-factor authentication, macro restrictions, and application control eliminate the first stage entirely.
• Apply least privilege. A standard user account does not prevent this specific exploit, but it removes the far easier escalation paths attackers try first.
• Enable hardware-backed protections. Virtualisation-based security, hypervisor-protected code integrity, and Secure Boot raise the cost of turning kernel code execution into persistence. These require TPM 2.0 and modern firmware — a concrete reason to retire endpoints that cannot support them.
• Prefer business-class hardware with firmware management. Platforms with vPro or equivalent expose remote firmware updating, hardware-rooted attestation, and out-of-band recovery.

That last point is where hardware selection and security policy meet. Machines such as the HP EliteBook 840 G11 with Core Ultra 5 125U and vPro and the Dell Pro 16 Plus PB16250 with vPro ship with TPM 2.0, verified boot chains, and manageability features that make virtualisation-based security practical to deploy at scale rather than merely available in theory. If you are unsure whether your current endpoint fleet supports VBS and HVCI, or you want an inventory-based assessment of which machines can be hardened and which need replacing, you can request a free quote from our team and we will walk through it with you.

Connecting the Threads

Read together, these three stories describe a single economy. AI training clusters consume DRAM wafers, which raises the price of the memory in your laptop. The same demand pulls foundry capacity toward leading-edge nodes, which is why a 2 nm consumer chip arrived alongside a price increase rather than the traditional price cut. And the value concentrated in those machines — the credentials, the models, the proprietary data now sitting on local storage rather than in a cloud tenancy — is exactly what makes a kernel privilege-escalation bug worth a nation-state's development budget.

For a buyer, the practical synthesis is straightforward. Specify memory and storage generously now, because they will not get cheaper this cycle. Treat NPU capability as insurance on a three-to-five-year horizon rather than as a feature you will use next Tuesday. And weight platform security — TPM 2.0, verified boot, firmware manageability — more heavily than you did three years ago, because the exploitation window has shrunk faster than most patch processes have.

Glossary of the Week

Setup at a Glance

Every device below was verified in stock in our catalogue at the time of writing. Stock moves quickly; the product page shows live availability.

Sources & Further Reading

Memory and pricing: Tom's Hardware — IDC expects average PC prices to jump by up to 8% in 2026; Tom's Guide — RAM price crisis live updates; IDC — Global memory shortage crisis: market analysis; Data Center Disk — the 2026 memory chip shortage. Apple M6 Mac mini: TechCrunch; 9to5Mac; Macworld. Patch Tuesday and CVE-2026-68820: SecurityWeek — August 2026 Patch Tuesday; SecurityWeek — Windows zero-day exploited in North Korean cyberattacks; The Hacker News; Help Net Security; CrowdStrike patch analysis; Rapid7. Radar items 4, 6, 7, 8, 9 and 10: Tech Startups daily briefing, August 25, 2026, citing Reuters, Axios, The Verge, The Wall Street Journal and Ars Technica. Samsung Micro RGB: Samsung Newsroom; CE Pro. Photos: Unsplash (free commercial license).

One Last Thing

If you are planning a hardware refresh this autumn, this is an unusual quarter in which waiting is not obviously the cheaper option. Memory and storage are the two components whose prices are climbing fastest, and they are also the two you cannot retrofit into a modern thin laptop. Whether you need one machine or two hundred, we are happy to build the configuration list with you, check live stock, and be candid about where spending more genuinely buys you something and where it does not — request a free quote from our team and we will get back to you with real numbers.

Written in Montreal on August 26, 2026. Specifications, prices and availability are accurate to the best of our knowledge at the time of publication and are subject to change.